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typedefs for uvm_event_pool and uvm_barrier_pool missing

September 6, 2014, 11:39 am
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Similar to the issue reported in [1], the typedefs for uvm_event_pool and uvm_barrier_pool are missing in the class reference document.

 

There is only a rather informal statement made in the section uvm_object_string_pool #(T)  stating that the uvm_event_pool is a uvm_object_string_pool storing uvm_events, and
uvm_barrier_pool is a uvm_obejct_string_pool storing uvm_barriers.

 

Instead, I propose a formal defintion in a global typedefs section.

 

Thanks,

Martin

 

 

[1] http://forums.accellera.org/topic/1992-typedef-for-uvm-report-cb-missing/

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Issues while migrating from uvm-1.1 to uvm-1.2

August 25, 2014, 4:50 am
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i was migrating from uvm-1.1 to uvm-1.2. In the release note, it's mentioned that :


==============================================================================


Topic: Migrating code using UVM 1.2

 

To ease the process of migrating code to UVM 1.2,

the old (incorrect) behavior remain available.

To restore the old behavior, it is necessary to define

the `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR symbol when compiling the UVM library:

 

| % ... +define+UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR uvm_pkg.sv

==============================================================================

 

even after doing this i am getting below warning :

==============================================================================


UVM_WARNING /remote/vip/apps/UVM/uvm-1.2/uvm-1.2/src/base/uvm_resource.svh(1416) @ 0.00 ps: reporter [uVM/RSRC/NOREGEX] a resource with meta characters in the field name has been created "device0.satasvc_device_vars"

UVM_WARNING /remote/vip/apps/UVM/uvm-1.2/uvm-1.2/src/base/uvm_resource.svh(1416) @ 0.00 ps: reporter [uVM/RSRC/NOREGEX] a resource with meta characters in the field name has been created "device0.satasvc_device_vars.xport0"

==============================================================================

 

These are the warnings from library(when no macro is passed during compilation):

==============================================================================


`ifndef UVM_NO_DEPRECATED

begin

for(int i=0;i<name.len();i++) begin

if(name.getc(i) inside {".","/","[","*","{"}) begin

`uvm_warning("UVM/RSRC/NOREGEX", $sformatf("a resource with meta characters in the field name has been created \"%s\"",name))

break;

end

end

end

 

`endif 

==============================================================================


 


Passing UVM_NO_DEPRECATED during compile time is wrong idea, because this macro is used in others files in library too, and i dont have any idea, what this macro does.

Please suggest me how to get rid of these warnings. 

 

Thanks

 

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uvm recording in base sequence

September 26, 2014, 11:47 am
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There is a new API to turn off recording in the base sequence from the driver:

is_auto_item_recording_enabled().  

But it is only applied at the item level.  The sequence itself is still recorded (in the start() task) regardless this switch. Should this switch be applied there as well?

 

Also it seems to me recording a sequence is not quite useful.  There is not much information contained in the sequence except it establishes a linkage with the sequence items.  I have encountered an issue with the way sequence recording done currently: once the body() task exit, the "recorder" for the sequence is gone.  But if driver (pipelined driver) want to recording the original sequence item UVM will generate runtime error.  The workaround from me is to implement some kind of mechanism to flush the driver (in my case, driver is DMA engine, and wait all completions comeback).

 
 
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NCVerilog compilation with UVM 1.2

September 29, 2014, 10:40 pm
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Hi All,

 

I'm trying to migrate to UVM 1.2 from 1.1d,

but I got the compilation error with NCverilog 12.10,

 

`define uvm_message_add_tag(NAME, VALUE, ACTION=(UVM_LOG|UVM_RM_RECORD)) \

ncvlog: *E,EXPRPP (xxx/UVM/uvm-1.2/src/macros/uvm_message_defines.svh,488|55): expecting a right parenthesis to close the formal

arguments to a macro [16.3.1(IEEE)].

 

Looked at systemverilog code in vm_message_defines.svh :488,

I'm wondering whether NCverilog could support this syntax with version 12.10 ?

 

Does UVM 1.2 have any restriction or documentation about the simulator version support ?

 

Thanks.

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Grabed sequence interrupts the separated access order of register

October 17, 2014, 4:45 pm
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hi,

 

when the register width differs from  the bus width and one register access results in a series of bus transactions，such as

 

using  32bit-width data bus  can access  64-register dut  by separated  two times，this  can be  interrupted by grabed

 

sequence，such as interrrupt sequence,  A example of   transaction_order   may be 

 

    A_upper( upper 32 bit of  A register，suppose higher priority  )  -----> Interrupt service sequence(may be access interrupt clear or mask  register (two times )   ----->  A_Lower( lower 32 bit of A register)

 

   whether  the transaction order  is corrected  or not  ?   this may cause some unright something?,thank you  :)

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Disable auto_item recording don't apply to uvm_reg_map

October 28, 2014, 9:30 am
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Hi,

when I comile my testbench, automatic item recording has been turned off by defining UVM_DISABLE_AUTO_ITEM_RECORDING.

a) set  m_auto_item_recording to 0 in uvm_sequencer_base.svh, if call the function of is_auto_item_recording_enabled(),it return  0

`ifdef UVM_DISABLE_AUTO_ITEM_RECORDING
  local bit m_auto_item_recording = 0;
`else
  local bit m_auto_item_recording = 1;
`endif

  // Access to following internal methods provided via seq_item_export

  virtual function void disable_auto_item_recording();
    m_auto_item_recording = 0;
  endfunction

  virtual function bit is_auto_item_recording_enabled();
    return m_auto_item_recording;
  endfunction

b)the follow code should be bypassed  in finish_item task，if not , sequencer.end_tr(item)  can  triggger  end_event 。

    if (sequencer.is_auto_item_recording_enabled()) begin
      sequencer.end_tr(item);
    en

c)In  uvm_reg_map.svh, such as do_bus_write()  method,after finish_item is called, the access  proccess will be suspended  all the way, except that  end_event emitted,

    bus_req.set_sequencer(sequencer);
      rw.parent.start_item(bus_req,rw.prior);

      if (rw.parent != null && i == 0)
        rw.parent.mid_do(rw);

      rw.parent.finish_item(bus_req);
      bus_req.end_event.wait_on();

d)   automatic item recording has been turned off by defining UVM_DISABLE_AUTO_ITEM_RECORDING ,The  user must  call  the  end_tr function  of the uvm_driver to  trigger end_event ?

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uvm_cmdline_processor - why its methods are non-virtual?

July 1, 2014, 10:55 am
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Hello,

  Recently a customer wanted a tweak to the way +UVM_* arguments are processed. Without going into details (not all are with me yet, am still asking them why they need it at first place), I could have achieved (at least I believe so) what the customer wanted by deriving my own cmd-line-processor class and overriding method like:

 

 function int get_arg_values (string match, ref string values[$]);
 
But I notice that this is non-virtual (and so are many other methods in there). Is there a good reason? If not, would the UVM 1.2 team consider making them virtual?
 
Also on a side note, the file uvm_cmdline_processor.svh doesn't use "extern" functions - maybe we should? Atleast for those lengthy ones? 
 
Thanks
Srini
 
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Dynamic Packed Array

December 17, 2014, 2:45 am
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Hello,

I have declared dynamic packed array in my .sv test file

 

logic [31:0] txdata [];

 

and I want to configure it to another variable in transaction block.

so, I am using  uvm_resource_db#(logic)::set("TEST_TO_TRANS","txdata_vip",vip_txdata,this); in test side and using statement  void'(uvm_resource_db#(logic)::read_by_name("TEST_TO_TRANS","txdata_vip",TXDATA)); in transaction side.

 

but It shows type error, so what should I use in #(type)??

 

 

 

 

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problem in if statement

February 24, 2015, 12:18 am
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gud mng all,

               In my systemverilog code, i have used if statement for giving different values to PWDATA in post randamization function. but only the first value is taken. i.e   32'hff300. but the select value is changing, but it does not get the PWDATA value. i am attaching the code here. pls help me to find me the error

 

 

 class my_seq_item_apb extends uvm_sequence_item;

  rand bit [15:0]  PADDR;
  rand bit [31:0] PWDATA;
  rand bit    [1:0]    mem_select;
 rand bit [5:0] select;            
                  
              constraint PADDR_mem { PADDR inside 
                                                {
                                                 16'h00, 16'h04,16'h08, 16'h0c,16'h10, 16'h14,16'h18, 16'h1c,16'h20,16'h24, 16'h28,16'h2c, 16'h30,16'h34, 16'h38,16'h3c, 16'h40,16'h44, 16'h48,16'h4c,16'h50, 16'h54,16'h58, 16'h5c,16'h60, 16'h64,16'h68, 16'h6c,16'h70
                                              };
                                                if(mem_select==2'b00)
                                                 {
                                                 PADDR inside{16'h20,16'h24, 16'h28, 16'h30,16'h34} 
                                              };
                                                else if (mem_select==2'b01)
                                                 {
                                                 PADDR inside {16'h20,16'h4C, 16'h3C, 16'h58,16'h5C}
                                              };
                                                else if (mem_select==2'b10)
                                                 {
                                                 PADDR inside {16'h20,16'h60, 16'h64, 16'h6C,16'h70}
                                              };
                                                else if (mem_select==2'b11)
                                                 {
                                                 PADDR inside {16'h20,16'h38, 16'h50, 16'h44,16'h48}
                                                 };
                                   } 
                   
                    `uvm_object_utils_begin(my_seq_item_apb) 
                   `uvm_field_int(PADDR,   UVM_ALL_ON)                                          
                   `uvm_field_int(PWDATA,  UVM_ALL_ON) 
                   `uvm_field_int(PRDATA,  UVM_ALL_ON)                                          
                   `uvm_field_int(mem_select,  UVM_ALL_ON)                                      
                   `uvm_field_int(PWRITE,  UVM_ALL_ON)                                          
               `uvm_object_utils_end     
               
               function new (string name = "my_seq_item_apb");
               super.new(name);    
               endfunction : new  
               
             
               function void post_randomize();  
             
            
               if (PADDR == 16'h20) PWDATA[0] = 1'b1;
                 
                  else if (PADDR == 16'h30 | PADDR ==16'h44 | PADDR ==16'h58 | PADDR ==16'h6c)
                  
                  begin
                      if (select==6'b000000 | 6'b110001 | 6'b110010 | 6'b110011 | 6'b110100)
                        begin
                    PWDATA[31:12] = 32'hff300;
                  end
                    else if(select == 6'b000001 | 6'b110101 | 6'b110111 | 6'b111000 | 6'b111001)
                      begin
                    PWDATA[31:12] = 32'hff380;
                  end
                    else if(select == 6'b000010 | 6'b111011 | 6'b111100 | 6'b111101)
                      begin
                    PWDATA[31:12] = 32'hff340;
                  end
                    else if(select == 6'b000011)
                      begin
                    PWDATA[31:12] = 32'hff3c0;
                  end
                    else if(select == 6'b000100)
                      begin
                    PWDATA[31:12] = 32'hff301;
                  end
                    else if(select == 6'b000101)
                      begin
                    PWDATA[31:12] = 32'hff381;
                  end
                    else if(select == 6'b000110)
                      begin
                    PWDATA[31:12] = 32'hff341;
                  end
                    else if(select == 6'b000111)
                      begin
                    PWDATA[31:12] = 32'hff3c1;
                  end
                    else if(select == 6'b001000)
                      begin
                    PWDATA[31:12] = 32'hff302;
                  end
                    else if(select == 6'b001001)
                      begin
                    PWDATA[31:12] = 32'hff382;
                  end
                    else if(select == 6'b001010)
                      begin
                    PWDATA[31:12] = 32'hff342;
                  end
                    else if(select == 6'b001011)
                      begin
                    PWDATA[31:12] = 32'hff3c2;
                  end
                    else if(select == 6'b001100)
                      begin
                    PWDATA[31:12] = 32'hff308;
                  end
                    else if(select == 6'b001101)
                      begin
                    PWDATA[31:12] = 32'hff388;
                  end
                    else if(select == 6'b001110)
                      begin
                    PWDATA[31:12] = 32'hff348;
                  end
                    else if(select == 6'b001111)
                      begin
                    PWDATA[31:12] = 32'hff3c8;
                  end
                    else if(select == 6'b010000)
                      begin
                    PWDATA[31:12] = 32'hff309;
                  end
                    else if(select == 6'b010001)
                      begin
                    PWDATA[31:12] = 32'hff389;
                  end
                    else if(select == 6'b010010)
                      begin
                    PWDATA[31:12] = 32'hff349;
                  end
                    else if(select == 6'b010011)
                      begin
                    PWDATA[31:12] = 32'hff3c9;
                  end
                    else if(select == 6'b010100)
                      begin
                    PWDATA[31:12] = 32'hff30a;
                  end
                    else if(select == 6'b010101)
                      begin
                    PWDATA[31:12] = 32'hff38a;
                  end
                    else if(select == 6'b010110)
                      begin
                    PWDATA[31:12] = 32'hff34a;
                  end
                    else if(select == 6'b010111)
                      begin
                    PWDATA[31:12] = 32'hff3ca;
                  end
                    else if(select == 6'b011000)
                      begin
                    PWDATA[31:12] = 32'hff310;
                  end
                    else if(select == 6'b011001)
                      begin
                    PWDATA[31:12] = 32'hff350;
                  end
                    else if(select == 6'b011010)
                      begin
                    PWDATA[31:12] = 32'hff390;
                  end
                    else if(select == 6'b011011)
                      begin
                    PWDATA[31:12] = 32'hff3c9;
                  end
                    else if(select == 6'b11100)
                      begin
                    PWDATA[31:12] = 32'hff3d0;
                  end
                    else if(select == 5'b011101)
                      begin
                    PWDATA[31:12] = 32'hff312;
                  end
                    else if(select == 6'b011110)
                      begin
                    PWDATA[31:12] = 32'hff352;
                  end
                    else if(select == 6'b011111)
                      begin
                    PWDATA[31:12] = 32'hff392;
                  end
                    else if (select==6'b10000)
                      begin
                    PWDATA[31:12] = 32'hff3d2;
                  end
                    else if(select == 6'b100001)
                      begin
                    PWDATA[31:12] = 32'hff311;
                  end
                    else if(select == 6'b100010 | 6'b101011 | 6'b101100 | 6'b101101 |6'b101111 | 6'b110000)
                      begin
                    PWDATA[31:12] = 32'hff351;
                  end
                    else if(select == 6'b100011 | 6'b100111 | 6'b101000 | 6'b101001 | 6'b101010)
                      begin
                    PWDATA[31:12] = 32'hff391;
                  end
                    else if(select == 6'b100100 | 6'b100101 | 6'b100110 )
                      begin
                    PWDATA[31:12] = 32'hff3d1;
                  end
                  else
                    begin
                 PWDATA[31:12] = 32'hff392;
               end
               end
               
                
                   else if (PADDR == 16'h34 | PADDR ==16'h48 | PADDR ==16'h5c | PADDR ==16'h70)
                   PWDATA[0] = 1'b1; 
               endfunction 
                  
     
 
 
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Getting field names of a packed struct

February 24, 2015, 6:12 am
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Hello,

         Does any one know of a feature in system Verilog to extract the field names of a struct and the order in which the field names appear in packed struct ?

Thanks..

↧

Suggestion: Built in Register test for INVALID ADDRESS access

July 1, 2015, 10:22 pm
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Hi ,

 

I would like to exchange the thoughts on built in sequences for register verification supports only accessing the valid registers.

 

Why should we not also expect to put some transaction other than valid address so to verify that bus should not hang ?

 

This is good thing and I think every verification engineer does himself in his verification setup. So I considered an important part this may be added to default UVM reg test seq library.

 

As per my understanding this can be achieved in two ways:

 

1. Adding dummy register for invalid address range. --> so in this case built-in reg_test sequences will pick them up for access

2. Manually make the bus transaction by providing invalid address.

3. Better way(Suggestion) --> In the register layer it should calculate the lowest and highest offset and if user enables the invalid address check (either from CONFIG_DB or CONFIG_FILE) it should create the transaction in the invalid range.

 

For 1 & 2 I have made the setup which is basically user effort.

 

For point 3. I expect your views to make efforts further.

 

Please suggest any better way if figured out !!

 

Great Many Thanks for your replies.

 

Please correct me if my assumptions/expectations are incorrect.

 

Thanks,

Karandeep

 

 

↧

UVM REG field-level report info message logging

August 14, 2015, 3:47 pm
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Hi,

 

It would be nice to add a UVM_HIGH level verbosity uvm_report_info message when register fields are accessed.  For example, after writing a register, it would be nice to see which FIELDs are written to and with what values.

 

Currently, there is a similar uvm_report_info message for the entire register.  It seems like having a similar message for FIELDs would be useful, since it is often the individual fields that we are interested in.

 

I know that users can add this themselves, but this seems like a generally useful addition.

 

Thanks,

Kelsey

↧

Problem with uvm_mem_region burst_read() task

November 14, 2014, 2:02 pm
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I think there's a bug in the UVM 1.2 burst_read() task of the uvm_mem_region class.

 

The "value" argument is defined as an output, not a reference, so an implementation of say a backdoor read cannot get the size of the value array to use to determine the burst size.

 

I believe this same bug was found and fixed in the burst_read() task of the uvm_mem class but the same fix is needed for the uvm_mem_region class burst_read().

 

Code snippets from UVM 1.2 for uvm_mem_region and uvm_mem shown below.  

 

Does anyone else agree it's a bug?

 

Thanks.

 

 

 

From uvm_mem_mam.svh

 

task uvm_mem_region::burst_read(output uvm_status_e       status,

                                input  uvm_reg_addr_t     offset,

                                output uvm_reg_data_t     value[],

                                input  uvm_path_e         path = UVM_DEFAULT_PATH,

                                input  uvm_reg_map        map    = null,

                                input  uvm_sequence_base  parent = null,

                                input  int                prior = -1,

                                input  uvm_object         extension = null,

                                input  string             fname = "",

                                input  int                lineno = 0);

 

 

From uvm_mem.svh

 

task uvm_mem::burst_read(output uvm_status_e       status,

                         input  uvm_reg_addr_t     offset,

                         ref    uvm_reg_data_t     value[],

                         input  uvm_path_e         path = UVM_DEFAULT_PATH,

                         input  uvm_reg_map        map = null,

                         input  uvm_sequence_base  parent = null,

                         input  int                prior = -1,

                         input  uvm_object         extension = null,

                         input  string             fname = "",

                         input  int                lineno = 0);

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Inconsistency in description of 'uvm_reg_item'

September 23, 2015, 2:42 am
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The class reference states the following for the 'value' field:

 

The value to write to, or after completion, the value read from the DUT.  Burst operations use the values property.

 

Even though 'value' is an array (and is shown as that in the definition), the wording gives the impression that it's a scalar value. Also, the text makes reference to a non-existing 'values' property.

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Shadow copy vs Active copy implementation in RAL

November 30, 2015, 3:34 am
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Hi,

 

i am looking for a solution to implement a RAL which supports both shadow coy and active copy as used by RTL.

 

Basically when a write happens to a particular register, the shadow copy gets updated and based on another register write (update) the shadow copy becomes the active copy.

 

In RTL, the registers are stored in two different signals and is assigned based on the extra signals which gets asserted based on the update.

 

please share some thoughts on implementing same.

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[RAL] Same register behaving differently based on another register

November 30, 2015, 3:40 am
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I have a situation where in the IP provided provided IPXACT for the same register with different behavior.

 

Eg: REG B which decides behaviour of REG A

      bit               FIELD D

 

    I)  REG A

      bit [4:0]        FIELD B 

    

    II)  REG A

      bit [10:0]      FIELD C

 

The reg A behaves like I) when REG B is programmed as 0 and ii) when REG B is programmed to 1.

 

Can you please share thoughts on best ways of implementing this. ?

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Bug in uvm_sequencer_base::grant_queued_locks();

December 1, 2015, 1:06 pm
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I discovered this issue when multiple sequences attempted to perform a lock() at the same time (not at all uncommon at the beginning of time when all sequences are launched). In 1.1d, the grant_queued_locks() function has a loop with the following comment:

    // Grant the lock request and remove it from the queue.
    // This is a loop to handle multiple back-to-back locks.
    // Since each entry is deleted, i remains constant

This loop is missing in 1.2. In fact, the whole function looks to have been re-written entirely. To start, I noted that if I simply replaced the 1.2 code with the 1.1d code, the test passes.

 

In 1.2, the second begin block in grant_queued_locks() starts out like this:

  // now move all is_blocked() into lock_list
  begin
	uvm_sequence_request leading_lock_reqs[$],blocked_seqs[$],not_blocked_seqs[$];  
	int q1[$];
	int b=arb_sequence_q.size(); // index for first non-LOCK request
	q1 = arb_sequence_q.find_first_index(item) with (item.request!=SEQ_TYPE_LOCK);
	if(q1.size())
		b=q1[0];  
	if(b!=0) begin // at least one lock
		leading_lock_reqs = arb_sequence_q[0:b-1]; // set of locks; arb_sequence[b] is the first req!=SEQ_TYPE_LOCK

Note the variable 'b'. It starts out as being the size of a queue, but then changes to an index in the arb_sequence_q variable. If that index happens to be 0, then the 'at least one lock' if statement won't be true. This is a real issue.

 

I'm going to try to find a patch that fixes it, but unless somebody here has an objection, I'll be submitting it to the Mantis page shortly.

 

 

 

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Typo in UVM Guide - TLM abstraction

February 17, 2016, 1:35 am
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Hi.
 
In uvm_users_guide_1.2.pdf, section "2.2 TLM, TLM-1, and TLM-2.0":
In practice, TLM refers to a family of abstraction levels beginning with cycle-accurate modeling, the most abstract level, and extending upwards in abstraction as far as the eye can see.
 

 

 

The 'cycle-accurate modeling' is not 'the most abstract level'...

 

Should be something like:
beginning with cycle-accurate modeling, the least abstract level,
 

 

 

Thanks,

Zvika

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UVM1.2 can report that run is not a task-based phase

June 3, 2016, 7:17 pm
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Under the right circumstances, UVM 1.2 can report an error such as this one:

'uvm_test_top.some_sequence' attempted to raise on 'run', however 'run' is not a task-based phase node! (This is a UVM_PHASE_IMP, you have to query the schedule to find the UVM_PHASE_NODE)

This is perplexing because obviously, run is a task-based phase, and one might think that UVM is off its rocker. But the real issue is what is found in the parentheses.

 

This came up while migrating a codebase to 1.2 (not the funnest of tasks, thank you very much). The user had this code working in 1.1d:

   some_sequence.set_starting_phase(uvm_run_phase::get());

Now, however, that get() call returns a UVM_PHASE_IMP and not the NODE itself. Most users probably don't care about the difference between these, as it has nothing to do with finding RTL bugs.

 

In any case, the above code must be replaced with something like this so that the NODE is used instead:

some_sequence.set_starting_phase(uvm_domain::get_common_domain().find(uvm_run_phase::get()));

This is not exactly the prettiest solution, but it seemed to work for me.

 

Can anyone suggest a better solution?

 

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get_uvm_args - a typo in the UVM class reference manual

June 21, 2016, 11:16 am
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Hi,

 

I would like to report a typo in the UVM class reference manual.

 

P.748

get_uvmargs
This function returns a queue with all of the uvm arguments that were used to start the
simulation. A UVM argument is taken to be any argument that starts with a - or + and
uses the keyword UVM (case insensitive) as the first three letters of the argument.

 

get_uvmargs should be get_uvm_args, missing a _

 

Horace

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